Real time fractal image coder based on characteristic vector matching

In this paper a new hardware method for fast and low power fractal coding is presented. The introduced method is based on binary classification of domain and range blocks. The technique not only reduces power consumption and increases processing speed but also has minimal effect on the degradation of the output result compared to the available fractal techniques. In order to show the functionality of the proposed algorithm, the architecture was implemented on a FPGA chip. It was further shown that the power consumption is reduced by the proposed architecture. The resulted compression ratios, PSNR error, gate count, compression speed and power consumption are compared against the existing designs. Applications of the proposed design in certain fields such as mass volume database coding are also discussed.